Register

Consider reg A,B

How to declare the address for this register as 100,110?

In reply to Design Engineer:
I thought this question was previously answered.
Is this what you meant?
// Consider 2 register namely A,B
// I need to define the address for the register as 0x102,0x104


module m(input  logic clk, rd, wr, 
         input  logic[15:0] addr, data, 
         output logic[15:0]data_out); 
     
     logic[15:0] A, B; 
    
     always  @(posedge clk)  begin 
         if(wr && addr==16'H102) A<=data; 
         if(rd && addr==16'H102) data_out<= A; 
         if(wr && addr==16'H104) B<=data; 
         if(rd && addr==16'H104) data_out<= B; 
     end            
 endmodule  

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
  4. FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy

In reply to ben@SystemVerilog.us:

Thanks a lot @Ben
It helps me a lot