Regarding SV Assertion

In systemverilog assertions, what is the difference when i am using “first_match” and “or” keyword.I am not getting it.

When you have a delay or a repeat operator you essentially have an ORing of sequences. Thus,
A ##[1:2] b // is same as
(A ##1 b) or (A ##2 b) //_sequencial ORing

A ##1 [*1:2] b // is same as
(A ##1b) or (A ##1 b ##2 b)
In both of these cases, you can have multiple matches. In an antecedent, all matches must be tested before the assertion terminates.
Thus, you need a first_match.
Do a search on first_match and my name, as I posted several replies on this issue.
Ben Cohen SystemVerilog.us