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  • Regarding goto and non consecutive repetition

Regarding goto and non consecutive repetition

SystemVerilog 5107
#SVA 51
rag123
rag123
Full Access
148 posts
February 15, 2021 at 5:37 pm

Hi,

I was playing around this piece of code with goto and non-consecutive. I noticed that this assertion never fails. I used strong and it failed when ack is 0. My question is lets say, if i want to check for each req, i need two ack's. In that case i am assuming i need to store the ack in a local variable and reset it whenever ack becomes 2? Is my understanding correct?

// req !ack !ack ack !ack !ack ack
 
property req_ack;
  @(posedge clk) $rose(req) |=>  (ack[->2]);
endproperty
 
or 
 
// req !ack !ack ack !ack !ack ack !ack
 
property req_ack;
  @(posedge clk) $rose(req) |=>  (ack[=2]);
endproperty

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ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2038 posts
February 15, 2021 at 8:05 pm

In reply to rag123:

/*  My question is lets say, if i want to check for each req, i need two ack's. 
    In that case i am assuming i need to store the ack in a local variable and reset it 
    whenever ack becomes 2? Is my understanding correct? */
// req !ack !ack ack !ack !ack ack
 
//[Ben] It depends upon what you mean. 
    // the following states any req requires 2 ack, but those are not individualized. 
    // Thus, the sequence  req ##1!req ##2 Req ##2 ack ##2!ack ##5 ack  
    // satisfies the two req's
property req_ack;
  @(posedge clk) $rose(req) |=>  strong(ack[->2]);
endproperty

// If you see uniqueness (every req gets 2 acks) see my replies at
https://verificationacademy.com/forums/systemverilog/assertion-req-and-gnt-signals

Ben Cohen
http://www.systemverilog.us/
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
...
1) SVA Package: Dynamic and range delays and repeats https://rb.gy/a89jlh
2) Free books: Component Design by Example https://rb.gy/9tcbhl
Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
3) Papers:
- Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment

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