Hello all,
I want to know that can we have Refrence models which works at pin level(interface) designed in SystemVerilog in a UVM bench?
What would be its disadvantages compared to that of the transaction based models?
Thank You
Hello all,
I want to know that can we have Refrence models which works at pin level(interface) designed in SystemVerilog in a UVM bench?
What would be its disadvantages compared to that of the transaction based models?
Thank You