Hi All,
I built a reference model for verification of a HDL design using UVM in SystemVerilog. I would like to reuse the reference model as a software emulator of the design. Is it possible to convert or wrap the SystemVerilog code into Python, C++ or .Net to get DLL file?
Thank you!
In reply to o.malnasi:
Of course it’s possible—it’s just software! I’ll have to admit most of the time I see people doing the reverse; integrating a C/C++ reference model with a UVM SystemVerilog testbench.
The question you should be asking is it practical? How much effort would it take to wrap the SystemVerilog model versus re-writing it?
It’s impossible for someone else to answer this for you without more details about the model (i.e. level of timing accuracy, independence of the reference model from the rest of the testbench). you may want to take a look at my DVCon paper: Easy Steps Towards Virtual Prototyping using the SystemVerilog DPI.
In reply to dave_59:
Thank you for the reply! I started to investigate about the topic, but I have things, which are unclear.
Yep, I mostly found articles about integration of a C/C++/Python model into SV verification environment, but not the other way around.
I would like to build a SW emulator, which exactly does the same thing as the SOC. My idea would be to integrate only the SV reference model (without the checks, scoreboard) in some SW emulator possibly with DPI-C. I would not do the job again and implement the system in an other language since I already implemented the reference model in SV. The model is cycle accurate.
What would be the method to encapsulate the ref model in a C environment, that does not need a simulator for running? Or do you think would it be easier to convert the reference model into Python manually?
In reply to o.malnasi:
I’m not aware of any tool that would let you compile UVM code and execute it without a simulator.