Rebind the connection at run time

SystemVerilog
,
1

Hi,

I have a question regarding rebinding of already connected module.

For Ex:


module DUT1(wire a1);
endmodule : DUT1

module DUT2(wire a2);
endmodule : DU2

module DUT3(wire a3);
endmodule : DUT3

module top();

  wire connect_a1_and_a2;
  wire connect_a1_and_a3;

  DUT1 dut1(.a1(connect_a1_and_a2));
  DUT1 dut2(.a2(connect_a1_and_a2));
  DUT1 dut3(.a3(1'b0));

endmodule : top

In above code, dut1 is connected to dut2 through connect_a1_and_a2 binding.
Now, I want to disconnect this connection at run time and reconnect dut1 to dut3 using connect_a1_and_a3 wire.

How can I re-bind the module connection at run time?

–
Regarding

2

You cannot change a module connection at runtime. You can change the behavior by inserting logic in between the modules, just like an RTL designer would do if they wanted to dynamically route signals. You also do this by creating the appropriate monitors and drivers in your testbench, but that might be less efficient.

3

In reply to dave_59:

Correct me if I got wrong, “Inserting logic in between the modules” means adding ifdef and elsif logic, right?

Is there any other logic affect module instantiate procedure?

4

In reply to electron:

No. By logic I mean you don’t connect any DUT directly with a single wire. You use something like a MUX. Talk to a hardware designer.

5

In reply to dave_59:

Sure, Thanks for guidance.