i’m tryin to make a SV code with the following bloks:
-Gaussian nois generator: the output is 16 bit, but i had converted it to real
-Low pass filter input real, output real
=> the verification of the two bloks are OK
-sigma delta modulator, input Real, Output bit
=> the connection between this blok with the Low pass filter is KO, this warning appear: ** Warning: (vsim-3015) valid_gng_low_pass_SDM.sv(17): [PCDPC] - Port size (64 or 64) does not match connection size (1) for port ‘Ain’. The port definition is at: SDM2.sv(2).
when i had changed the output of the gaussian noise generator from bits to real it appear to work, but when connect with SDM, it is failing, i do not know why
Hi saketa. It would be helpful if you would post the port definitions for valid_gng_low_pass_SDM.sv and SDM2.sv, as well as the code that instantiates the modules and connects the ports. On the surface this looks like Verilog’s implicit-wire-is-really-a-typo “feature”.
In reply to saketa:
Hi saketa. It would be helpful if you would post the port definitions for valid_gng_low_pass_SDM.sv and SDM2.sv, as well as the code that instantiates the modules and connects the ports. On the surface this looks like Verilog’s implicit-wire-is-really-a-typo “feature”.
Hi sbellock: module sdm_rnm (input bit clk_1mhz, input real Ain, output bit Dout); //SDM2
module valid_gng_low_pass (clk, rstn, ce, Fp, Av, OUT, valid_out);
output real OUT; // output of filter
input logic clk;
input logic rstn;
input logic ce;
input real Fp; // corner frequency (Hz)
input real Av;
output valid_out;
//local signal//
real data_out;
module valid_gng_low_pass_SDM (clk, rstn, ce, Fp, Av, Dout, valid_out);
input logic clk;
input logic rstn;
input logic ce;
input real Fp; // corner frequency (Hz)
input real Av;
output bit Dout;
output bit valid_out;
real data_out;
valid_gng_low_pass U2_valid_gng_low_pass (.clk(clk), .rstn(rstn), .ce(ce), .Fp(Fp), .Av(Av), .OUT(OUT), .valid_out(valid_out));
sdm_rnm U3_sdm(.clk_1mhz(clk), .Ain(OUT), .Dout(Dout));
endmodule
Thank you sbellock, but it solve the warning not the expected result the simulation is giving for GNG+LowPass+SDM a Dout=0, i was expecting a stream of bits
here is the testbench i’m using:
`timescale 1 ns / 1 ps
module tb_gng_low_pass_SDM;
// Parameters
parameter ClkPeriod = 1000.0;
parameter Dly = 1.0;
parameter N = 1000000;
// Local variables
logic clk;
logic rstn;
logic ce;
real OUT;
real Fp; // corner frequency (Hz)
real Av;
logic Dout;
logic valid_out;
// Instances
valid_gng_low_pass_SDM u_valid_gng_low_pass_SDM (.clk(clk), .rstn(rstn), .ce(ce), .Fp(Fp), .Av(Av), .Dout(Dout), .valid_out(valid_out));
// System signals
initial begin
clk <= 1'b0;
forever #(ClkPeriod/2) clk = ~clk;
end
initial begin
rstn <= 1'b0;
#(ClkPeriod*2) rstn = 1'b1;
end
// Main process
int fpOut;
initial begin
fpOut = $fopen("gng_data_out.txt", "w");
ce = 0;
#(ClkPeriod*10)
repeat (N) begin
@(posedge clk);
#(Dly);
ce = 1;
Fp = 2000;
Av = 2;
end
@(posedge clk);
#(Dly);
ce = 0;
#(ClkPeriod*20)
$fclose(fpOut);
$stop;
end
// Record data
always_ff @ (negedge clk) begin
if (valid_out)
$fwrite(fpOut, "%0d\n", OUT);
end
endmodule