Real to int conversion

SystemVerilog
1

Intention to get the rounded value for both positive and negative value. collect real data type and equal to integer data type will get rounded value
Ex: In negative
-14.6 to -15.5 => -15
Ex: In positive
14.5 to 15.4 => 15

Actually in case some time in positive 15.5 its rounding with 15 but its working perfect for 16.5 rounding with 17
is there any behind logic is there for these conversion?

2

In reply to christo97:

Rounding fractional 0.5 part is supposed to be away from 0.

You need to show us an example piece code that demonstrates what you are seeing versus what you expected. Floating point math can give you lots of unexpected results.

module top;
  real a,b;
  initial begin
    a = 14.0;
    b = 0.1;
    repeat(5) a = a + b;
    $display(a);
    $display(a ==14.5); // not equal due to rounding errors
    $display("%10.30f",a);
  end
endmodule