Re-triggering of always block

SystemVerilog
,
1

Hi All,

I was trying to check internal signals of DUT, signal under consideration is a packed array.
I wanted to check number of change in value of this signal. let the signal be reg[49:0] a;

I created an interface and using bind construct connected to the signal inside DUT.

interface (input [49:0] a );
  int count;
  always @(a) count++;
endinterface

The always block gets triggered at same time twice?? I am not able to find the reason for this behaviour.
I have added print statement inside always block with value of “a” and $realtime, I get two prints with same value and time. Without change in value how can the always block trigger again that too @ cannot capture event in same time if event is triggered before??

2

In reply to verif4life:

If the signal or part of the signal gets assigned multiple times with with a delta delay (#0) or non-blocking assignment between writes, you will definitely see multiple triggers with the same timestamp. If different bits of the signal is written from different places at the same time, there’s no way to guarantee only one triggering of the always block.

A better approach would be introducing a sampling clock and look at changes from clock to clock

interface (input [49:0] a, input bit clk);
  int count;
  always @(posedge clk) if ($changed(a)) count++;
endinterface