This was a question posted to me.
// after a, then between 2 pulses of b, c & d are asserted
ap_abcd: assert property(@ (posedge clk)
$rose(a) |-> (c[->1] and d[->1]) intersect
$rose(b)[->2]);
Test code; http://systemverilog.us/vf/bc_between.sv
Ben Cohen
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