Randomizing field depending on the previous transaction

SystemVerilog
,
1

In my sequence, I call

uvm_create(item) item.randomize with { trans_type inside {READ, WRITE}; }; uvm_send(item)

I want to send a READ transaction immediately after a WRITE transaction every time. How do I achieve that ?

2

What you need to do is randomize the same item repeatedly and send its clone. You can use a const cast to have the solver treat the expression as a constant value, the value it had before calling randomize().

`uvm_create(item)
repeat( some_number) begin
        item.randomize with { trans_type inside {READ, WRITE}; 
                              const'(trans_type) == WRITE -> trans_type == READ;};
       `uvm_send(item.clone())
      end
3

In reply to AMARDEEP R PALURU:

Thinking loud about your problem statement - won’t you need the address and other related fields also to be same as previous transaction? If yes I suggest you simply do:

// after first uvm_send
if (trans_type == WRITE)
begin
req.trans_type = READ;
uvm_send(req)

Regards
Srini

P.S. Lazy syntax as I am on mobile

4

In reply to dave_59:

Dave,
I didn’t understand two things. Why are we randomizing it multiple times and why to clone before sending ?

5

In reply to AMARDEEP R PALURU:
You didn’t explain your situation very well, and I was just assuming you are sending multiple random transactions in a some kind of a loop. You need to explain your sequence fully if that doesn’t help you.

The reason you need to clone the transaction is because `uvm_send just passes a handle to the sequencer which it eventually passes to a driver. Both the sequencer and driver modify fields of your transaction and if you sent the same handle multiple times, they would overwrite each other.