Randomize address equal to 2 to the power of values

SystemVerilog
,
1

SystemVerilog randomize address equal to 2 to the power of value?
addr = 1, 2, 4, 8, 16, … 32,
I am generation above values using systemverilog constraints
below is the code:

class two_power_addr;
 rand bit [14:0] addr;
      bit [14:0] temp;
  constraint c_addr {addr == temp;}
endclass
module tb();
  two_power_addr c;
initial
  begin
    c=new();
    c.temp=16'h1;
    for(int i=0; i<15; i++) begin      
      c.randomize();
      c.temp=c.temp<<1;
     $display("%0d \n", c.addr);
    end
  end
endmodule

Instead of above the above constraint i am replacing below like this

class two_power_addr;
  rand  bit[14:0]    addr;
  rand  bit[14:0]    temp;
  constraint c_addr {temp == 2**addr;}
endclass

module tb();
  two_power_addr c;
initial
  begin
    c=new();
    repeat(20) begin
      c.randomize();
      c.randomize()with {addr<8;};
    $display("%0d \n", c.temp);
  end
  end
endmodule

both are working fine.
my doubt is instead of 2 to the power i am replacing 10 than it is showing error below like this
means i am changing constraint like this constraint c_addr {temp == 10**addr;}
Error-[IUORCE] Illegal operator in constraint
testbench.sv, 4
$unit, “(10 ** this.addr)”
The operator ** is not allowed in constraints.
Remove the operator or replace it with an expression allowed in constraints.
please provide the solution for above issue

2

In reply to anvesh dangeti:

Please use code tags making your code easier to read. I have added them for you.

This error message is incorrect—there is no such restriction. There’s even examples using it in the LRM. This Mentor sponsored public forum is not for discussing tool specific issues. Please read you tool’s user manual or contact your tool vendor directly for support.

3

the above logic for generating 2 to the power values. If any other constraint-logic is there. Please suggest me?

4

Hi,

You can find the below constraint for generating the values which are powers of 2.


class AB;
  rand bit[31:0] val;
  
  constraint power_of_2{ val != 0;
		        (val & (val-1)) == 0;} //bitwise AND operation
							
  function void post_randomize();
    $display("value is %0d", val);
  endfunction
endclass

Hope this helps.
Putta Satish

5

In reply to puttasatish:

Hi Satish,

How to achieve power of 3 scenario ?

Regards,

6

In reply to ranju2894:

  constraint c_addr {temp == 3**addr;}
7

In reply to dave_59:


class two_power_addr;
 rand bit [14:0] addr;
      bit [14:0] temp;
  constraint c_addr {temp == 3**addr;}
endclass
module tb();
  two_power_addr c;
initial
  begin
    c=new();
    for(int i=0; i<3; i++) begin      
      c.randomize();
      $display("output is %0d \n", c.addr);
    end
  end
endmodule

Hi Dave,

Is this what you are suggesting for power of 3?

I tried with Mentor Questa but it is not giving me expected output. Mostly incorrect logic.

8

In reply to edaboy:

temp needs to be declared with rand, and you need to place limits on addr to prevent overflow.