Randomization failure with Inline constraint

SystemVerilog
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1

Hi,

let’s say I have 3 variables a,b, and c in my item class. I want to solve c based on values of a and b. But I also provide an inline constraint when randomizing the item


class item;
rand int a, b,c;
constraint cst{
solve a before c;
solve b before c;
c == a+b;
}
endclass

class some_other_class;
item.randomize with {
c < 8;
}
endclass

In the above code will the simulator keep changing the values of a and b to satisfy the inline condition of a+b<8 ?

Thanks.

2

In reply to sj1992:

An inline constraint gets solved with all other constraints; there should not be a constraint failure here. Can you provide a complete example?

Also note that your are using int as a signed datatype that allows a large number of negative numbers in your solution space.

3

In reply to dave_59:

Hi Dave,

I made a mistake in my previous code. Here is the code


class item;
rand unsigned int a, b,c, d;
constraint cst{
solve d before b;
solve a before c;
solve b before c;
(d==0) -> b == 40;
c == a+b;
}
constraint cst_d{
d dist{
0:=10,
1:=80
};
}
endclass
 
class some_other_class;
item.randomize with {
c < 8;
}
endclass

Thanks.

4

In reply to sj1992:

The constraint c < 0 can never be true since c is unsigned. You would get the same constraint failure had you added that constraint directly into the class item.