Randomization differences using Ternary Operator

SystemVerilog
,
1

Hi all ,

I have a Sample Code ::



class Sub ;

rand bit [10:0] trans_length ;

endclass

class Main ;

bit user_data ;
bit [10:0] user_transfer_length ;
rand bit [10:0] transfer_length ;

Sub sub ;


task body();

void'( randomize(transfer_length) );

sub = new();

`ifdef TER // "TER"nary Operator
if ( sub.randomize with { trans_length == ( user_data == 1 ) ? user_transfer_length  : transfer_length ; } )
`else
if ( sub.randomize with { if ( user_data == 1 ) { trans_length ==  user_transfer_length ; } else {  trans_length == transfer_length ; } }  )
`endif 
 begin

   $display("Sucess with sub.trans_length == %0d && user_data == %0d ",sub.trans_length,user_data);
   $display(" user_transfer_length == %0d && transfer_length == %0d ",user_transfer_length,transfer_length);

 end

endtask

endclass


Main main ;

initial begin

main = new() ;

main.user_data = 0 ;
main.body();

main.user_data = 1 ;
main.user_transfer_length = 'd1024 ; 
main.body();

end

I Observe different results for +define+TER and without it . Can’t understand why ??

Output without +define+TER

Sucess with sub.trans_length == 1891 && user_data == 0
user_transfer_length == 0 && transfer_length == 1891
Sucess with sub.trans_length == 1024 && user_data == 1
user_transfer_length == 1024 && transfer_length == 245

Output with +define+TER

Sucess with sub.trans_length == 375 && user_data == 0
user_transfer_length == 0 && transfer_length == 1891
Sucess with sub.trans_length == 1381 && user_data == 1
user_transfer_length == 1024 && transfer_length == 245

Thanks ,

2

In reply to Have_A_Doubt:

You are missing ()'s Look at Table 11-2 Operator Precedence

3

In reply to dave_59:

Having referred ::
https://verificationacademy.com/forums/systemverilog/can-we-use-ternary-operator-constraints

The solution is ::


if ( sub.randomize with { trans_length == ( ( user_data == 1 ) ? user_transfer_length  : transfer_length  ) ; } )