Several issues:
- When you call std::randomize() on a variable, there are no constraints applied unless you pass them on the randomize() call:
success_rand=std::randomize(random_wr_data) with {constraint...};
- You can randomize the entire class instance to utilize the constraint C1 with:
if (!this.randomize()) `uvm_error("seq", "Randomization failed");
- To enable the class randomization, you need to add 'rand' to random_wr_data[].
Here is a working example:
import uvm_pkg::*;
`include "uvm_macros.svh"
class seq1 extends uvm_sequence;
`uvm_object_utils( seq1 )
bit[23:0] wr_addr ;
rand int random_wr_data[];
int rd_data[];
constraint C1 {
random_wr_data.size() == 'd17;
foreach(random_wr_data[i]) {
if (i==0) { random_wr_data[i][31:12] =='0 ; random_wr_data[i][0]=='b0; }
else if(i==1) { random_wr_data[i][31:13] =='0 ;}
else if(i==2) { random_wr_data[i][31:13] =='0 ; random_wr_data[i][11]=='b0; random_wr_data[i][0]=='b0; }
else if(i==3) { random_wr_data[i][31:16] =='0 ; }
else if(i==4) { random_wr_data[i][31:16] =='0 ; }
else if(i==5) { random_wr_data[i][31:15] =='0 ;}
else if(i==6) { random_wr_data[i][31:16] =='0 ; }
else if(i==7) { random_wr_data[i][31:9] =='0 ; }
else if(i==8) { random_wr_data[i][31:16] =='0 ; }
else if(i==9) { random_wr_data[i][31:14] =='0 ; }
else if(i==10) { random_wr_data[i][31:1] =='0 ; }
else if(i==11) { random_wr_data[i][31:14] =='0 ; }
else {random_wr_data[i][31:9]=='0 ; random_wr_data[i][7:4]=='0;}
}
}
function new(string name="seq" );
super.new(name);
endfunction
task body();
if (!this.randomize()) `uvm_error("seq", "Randomization failed");
`uvm_info("seq",$sformatf("Array has %d elements", random_wr_data.size()), UVM_NONE);
for (int i=0;i<=16;i++)begin
wr_addr = wr_addr + 'h4;
// do_write(wr_addr, random_wr_data[i]);
`uvm_info(get_type_name(), $sformatf("Write Address:%0h, Data=[%0h]",wr_addr,random_wr_data[i]),UVM_NONE)
// do_read(wr_addr, ccu_rd_data[i]);
`uvm_info(get_type_name(), $sformatf("Read Address:%0h, Data=[%0h]",wr_addr,rd_data[i]),UVM_NONE)
end
endtask// body
endclass
class test extends uvm_test();
`uvm_component_utils(test)
function new(string name="test", uvm_component parent = null);
super.new(name,parent);
endfunction
task run_phase(uvm_phase phase);
seq1 my_seq;
my_seq = seq1::type_id::create("my_seq");
my_seq.start(null);
endtask
endclass
module top();
initial begin
run_test("test");
end
endmodule
/systemverilog]
