In the following code (edaplaground):
- when we’re randomizing an array of plain bit, array size is randomized with array contents → no contradiction
- when we’re randomizing an array of structs, array size is randomized before array contents → occasional contradiction
Questions:
- What is the SystemVerilog rule that dictates this cross-simulator behavior?
- Is there a way to get the struct array to behave similar to the bit array? I’ve been adding a rand valid bit to each struct via a template class, but I wonder if there’s a better way.
module rand_lists();
typedef struct {
rand bit x;
} some_struct_t;
class rand_bit_array;
rand bit q[];
constraint c_q_size {
q.size() <= 5;
};
constraint c_q_val {
q.sum(item) with (32'(item)) == 5;
};
function new();
q = new[10];
endfunction
endclass
class rand_struct_array;
rand some_struct_t q[];
constraint c_q_size {
q.size() <= 5;
};
constraint c_q_val {
q.sum(item) with (32'(item.x)) == 5;
};
function new();
q = new[10];
endfunction
endclass
initial begin
rand_struct_array struct_array_i;
rand_bit_array bit_array_i;
bit_array_i = new();
bit_array_i.randomize();
$display("%p", bit_array_i.q);
struct_array_i = new();
struct_array_i.randomize();
$display("%p", struct_array_i.q);
end
endmodule