Randomization

SystemVerilog
1

I have seen an example in which the transaction class of SytemVerilog testbench was declared as random variable in generator class. what is the significance of this??

2

In reply to ulhaqsalman:

There is no significance to things we cannot see. Where did you see it?

3

In reply to ulhaqsalman:

I think you are referring to something like this. Here randomizing composite class (Here it’s Parent) also randomizes properties of instance of SomeClass as well, because its declared as rand.

   class SomeClass;
      rand bit [3:0] A;
      rand byte B;

      function void displayItems();
         $display("Class Items: A = %d, B = %d", A, B);
      endfunction
   endclass

   class Parent;
      rand SomeClass someClass = new(); //Remove rand here and see effects!
      
      function void display();
         someClass.displayItems();
      endfunction
   endclass


   Parent P;
   initial
   begin
      P = new();
      P.display();

      repeat(5)
      begin
         void'(P.randomize());
         P.display();
      end

      $finish;
   end