Randomization

SystemVerilog
, ,
1

How to randomize a variable it is not declared as rand/randc?

2

In reply to anvesh dangeti:

module top;
  bit Avariable;
  initial Avariable = $urandom;
endmodule
3

Pass the variable as argument to the randomize() call .
Eg :- obj.randomize(variable)

4

In reply to bl4ckp3rl :

Be careful with that advice. All constraints on obj still need to be honored.

It would help if the original question had more detail in what the motivation behind the question was.

5

I would suggest std::randomize([variable_list]) [with constraint_block]

Please refer to Section 18.12 of the IEEE standard.

6

In reply to dave_59:

Agree with Dave , i was thinking of following code


class   base;
  
  bit[2:0] addr;
  constraint c{addr ==4;}
endclass:base


module tb();
  
  base   base_h;
  initial
    begin
      base_h =new();
      base_h.randomize(addr);
      $display("contents %0d ",base_h.addr);
    end
endmodule