Randomization

SystemVerilog
,
1

when I randomize a variable I should get below sequence repeatedly.
“1,2,3,4,5” “1,2,3,4,5” could you please let me know the constraint-logic to get this.

2

In reply to anvesh dangeti:

class A;
 rand bit[2:0] n;
 constraint seq { if (const'(n)==5) 
                    n==1; else n==const'(n)+1; }
endclass
3

In reply to dave_59:
Hey Dave,
Can you briefly give the idea how this code runs?
When used without const keyword it does not yield the required result

4

In reply to bachan21:

When you are casting an expression using const’ the type of expression will be passed through unchanged.In this scenario the variable will retain the previous value of randomization.The following code generates the same sequence in Qn and almost mimics const’.


class    base;
  
  rand bit [2:0] addr;
  bit [2:0] hold;
  
  
  
  constraint const_mimic{if(hold ==5) // hold kept 5 so that max limit is 5 after that the sequence should start again from 1  ("1,2,3,4,5")
                         addr == 1;
                         else addr ==hold+1;
                        }
  
  
  function void post_randomize();
      hold  = addr;
  endfunction
  
endclass


module tb();
  
  base   b_h;
  
  initial
     begin 
       b_h =new();
       repeat(20)begin:loop
       if(b_h.randomize())
       $display("the contents %0d",b_h.addr);
       end:loop
     end
 
endmodule

HTH

5

In reply to bl4ckp3rl :

Thanks for explanation for casting with const

6

In reply to dave_59:

In reply to anvesh dangeti:

class A;
rand bit[2:0] n;
constraint seq { if (const'(n)==5) 
n==1; else n==const'(n)+1; }
endclass

Hi Dave,
I tried to generate the seq 1-2-3-4-5 using post_radomize since const is not supported in my tool. I initialized bit[2:0] prev_n =0;

Yet seq generated is 3-4-5-1-2-3-4-5.

How do I make sure seq starts with 1 not any other rand value?

Thanks!

7

In reply to UVM_SV_101:

Then you might as well not even use a random variable. Just use pre/post_randomize().