Random variable: constraint dist control

SystemVerilog
1

Hello forum gurus,

  1. I am having a situation where I need to generate a random enable signal, which is 1-bit. (rand bit enable)
  2. I want the signal to be x % off, for example, in 100 cycles, it should be 100 times x% cycles 0.
  3. further i would like to control the value of x in my testbench.

I tried to define a class like the following, and it won’t compile.

class my_rand;
rand bit enable;
int x = 0;

task set(x);
this.x = x;
endtask

constraint c1{
enable dist { 0: x , 1: (100 - x) };
}
endclass

how should I approach this problem?
Regards,
p

2

In reply to pepes:

It would help to show the syntax errors you were getting.

enable dist { 0:= x , 1:= (100 - x) };

would have worked.

Also, use functions instead of tasks for non-time consuming methods (methods that do not block)