Random variable that can retain value for few clocks

SystemVerilog
1

Hi,

I have a random 1 bit variable (valid) used in UVM sequence that needs to retain its value for 6 clocks whenever it is 1. It can be 0 for any number of clocks. I tried using weighted constraints but its not 1 for 6 clocks exactly all the time. How do I achieve that?

Thanks

2

In reply to saum8jan:

You are missing quite a few details. How does a clock cycle relate to the transaction you send as a sequence_item?