Random choose the behavior in the test

SystemVerilog
1

I have a simple requirement as below.

we have two tasks (task1 and task2) defined in the test. and what we just need to do is to randomly execute one or two of them in each loop. for example we have 256 times to loop and in each loop, we could run task1, could run task2 or could run both. How to implement it in the easiest way ?

2

In reply to zz8318:

You can use the randcase construct, and adjust the weights as you so desire.


randcase
    1: task1;
    1: task2;
    1: begin
        task1;
        task2;
    end
endcase