RANDCASE - Can randcase have if statement inside it?

SystemVerilog
,
1

I have seen in the system verilog reference that rand sequence can have if, repeat and so on.
Similarly can we have the conditional statements inside randcase?

Sample code below: Is it possible to have if statement inside randcase as shown below and is it mandetory to have an else condition ?

randcase
case1 : 1 ;
case2 : 2 ;
case3 : 3 ;
case4 : 4 ;
case5 : 5 ;
if (condition) begin
case6 : 6 ;
end
endcase

2

In reply to sruthikrapa:

No, randcase is just a standalone case-statement that randomly branches to a case item. Each case item can be one procedural statement, or a block statement. And that statement could be a procedural if-statement.

You can also think of randcase as a simple form of randsequence.

randcase
  1: task1;
  5: task2
 10: task3;
endcase

is equivalent to

randsequence ()
 RandomCase : {task1;} :=1 | {task2;} :=5 | {task3;} := 10;
endsequence