Race condition and Delta simulation time

SystemVerilog
, ,
1

Hello all,



module test;

  int a;

     initial 
       a = 1;
 
     initial 
       $display(a);

endmodule

The above code I declared two initial blocks, some simulator value is displayed as “0” and others it is “1”. this is happening due to “race condition” or “delta simulation time” concept?

2

In reply to SriGanesh D:

Yes.

3

In reply to cgales:

Is it due to “race condition” between two initial block.?

4

In reply to SriGanesh D:

Definitely a race condition, but not sure what you meant by “delta simulation time concept”. The fact that SystemVerilog schedules everything into a queue of active events in nondeterministic manner is called by some a “delta” cycle.

5

In reply to dave_59:

I meant the nondeterministic manner in active as “delta simulation time”. Thank you dave for the replay.