Queue

SystemVerilog
1 
module queue();
  int data, q_int[$]; // whether memory is allocated at this time during declaration
  bit [7:0] q_bit[$:100]; 

initial 
 begin
      q_int.push_front(0); // or this time
      q_bit.push_front(4); // or this time
 end
endmodule

question---->whether memory is allocated at during declaration or while using it(in our case push front())

2

In reply to santosh manur:

For simulation, every static variable declaration takes up some memory overhead as part of its declaration, but each element of the queue gets allocated dynamically when executing a procedural statement.

For synthesis, there needs to be memory(registers) allocated that holds the maximum number of elements.

3

In reply to dave_59:

but whatever written is inside module… right??

so is’nt it static by nature?

4

In reply to sujith r:

Not sure what your question is. Yes, the variables declared in the module above are static, but static variables can have dynamic elements.

5

In reply to dave_59:

In reply to sujith r:
Not sure what your question is. Yes, the variables declared in the module above are static, but static variables can have dynamic elements.

thank u… i understood now…