Quetsa - SystemVerilog Construct Usage Summary?

Hi,

I was wondering if there is a way by which Questa can report a summary of SystemVerilog constructs used in current project files ?
If not, is there any tool that does that ?

Thanks.

I do not know of a tool that can do this automatically for you.construct. If you mean keywords, there are many perl commands that could do this. Or you could write a VPI routine to decompile the source and count each kind of construct it finds.

But you really need to specify what you mean by a SystemVerilog construct. Each port in a port list could count as one construct, or the port list as a whole could count as a construct.

Thanks for the answer.
That was helpful.

Well, by construct I wish to count unique, let’s say keywords.
e.g.

genvar creat;
generate
for(create=0;create<ports;create+=1)
//Instance Here
endgenerate

always_ff
begin
//foo
end

always_comb
//foo
begin
end

assert@....

I wish to count usage of genvar, always_ff and always_comb, assert, etc, which are SV keywords for constructs.

I guess as you suggested, perl commands might help. Or maybe even grep.

However, is it possible to extract this from Questa/Modelsim?

Thank you!