In reply to rgarcia07:
There are no restrictions on setting the rand_mode() inside pre/post_randomize, but there could be some complications if you try changing the mode of a nested rand class object and the ordering of it calling the pre/post_randomize methods of those nested object. Probably not a good idea.
The current SystemVerilog LRM has some terminology problems left over from the Verilog, further complicated by features inherited from Vera.
In Verilog, a function must return a value as part of an expression, must have input arguments, cannot have any delays, and cannot be used as a bare statement. Tasks cannot return a value and can only be used as a bare statement. Vera, where much of the testbench features of SystemVerilog came from, did not really make any distinction between tasks or functions; they were just routines. Vera did take advantage of whether a routine had an argument or not to alter its behavior. That's something that carried into SystemVerilog, but SystemVerilog has no mechanism for the user to write such behavior.
Verilog uses the term "System task" to define what are now called void functions in SystemVerilog, and sometimes uses the terminology "called as a task" also to mean called as a void function. The LRM has to fix all these enigmas, but will take some time. https://accellera.mantishub.io/view.php?id=2027
