Question regarding constraint mode

SystemVerilog
1 
class con_mode;
  rand int b;
  constraint b_short {b inside {[1:32]};}
  constraint b_long {b inside {[75:150]};}
endclass

`include "con_mode.sv"
module top;
  con_mode cm;
  initial
  begin
    cm = new();
    repeat(5)
    begin
      cm.randomize();
      $display("The value of b is %0d",cm.b);
    end
      cm.b_short.constraint_mode(0);
      $display("THE SHORTER CONSTRAINT IS DISABLED");
      repeat(5)
      begin
        cm.randomize();
        $display("The value of b after disabling the shorter constraint is %0d",cm.b);
      end
  end
endmodule

In the o/p that I get :
For the line : $display(“The value of b is %0d”,cm.b);
The value of b is not getting randomized.
I want to know the reason.
I get the o/p as : The value of b is 0.
0 is the default value for the data type int.

2

In reply to Ravi007:
The two constraints b_short and b_long are conflicting. The first call to cm.randomize() fails, and cm.b retains the value it had before calling randomize().

You need to test the return value from randomize whenever there are active constraints.

3

Hi dav_59,
why the first call to cm.randomize() fails?
Please explain me sir,
Regards
Rajaraman R

4

In reply to Rajaraman Rak7:

because sv cant decide if to keep it within 1:32 or 75:150…


constraint b_short {b inside {[1:32]};}
  constraint b_long {b inside {[75:150]};}