Is there a way to update this interface so that I can access a interface signal from the driver or monitor though a modport and also the clocking block so that I can get the direction correct and also allow timing synchronization in that access? In its current form I can either access though a clocking block or through a modport but not both. Please suggest an alternate module top-level structure(which calls the run_test) if there is no way to do this directly within an interface so that I re-structure the setup accordingly.
interface ifc(input bit clk);
logic wrdata;
logic rddata;
logic write;
logic read;
logic reset;
logic add;
clocking cb @(posedge clk);
output wrdata, read, write, reset, add;
input rddata;
endclocking
modport driver (output wrdata, read, write, reset, add,
input clk, rddata);
modport monitor (input wrdata, read, write, reset, add,clk, rddata);
endinterface