Question on "Incompatible complex type assignment error"

SystemVerilog
1

Hi,
I have following piece of system verilog code :


function logic [15:0] calc_checksum (input logic[255:0] keyin);
  logic[15:0] sum_int_ar1[7:0];
  logic[15:0] sum_int_ar2[3:0];
  logic[15:0] sum_int_ar3[1:0];
  logic[15:0] sum_final;
  logic x [7:0][15:0];
  logic[15:0] y ;
  
  y = x[3][15:0];
  
  for (int i = 0; i <= 14; i = i+2) begin
    sum_int_ar1[i/2] = keyin[(16*i + 15) -: 16] + keyin[(16*i+31)-: 16];
  end
  for (int i = 0; i <= 6; i = i+2) begin 
    sum_int_ar2[i/2] = sum_int_ar1[i] + sum_int_ar1[i+1];
  end
  for (int i = 0; i <= 2; i = i+2) begin 
    sum_int_ar3[i/2] = sum_int_ar2[i] + sum_int_ar2[i+1];
  end
  sum_final = sum_int_ar3[0] + sum_int_ar3[1];
  return sum_final;

endfunction

I am getting following error “Error-[ICTA] Incompatible complex type
testbench.sv, 11
Incompatible complex type assignment
Type of source expression is incompatible with type of target expression.
Mismatching types cannot be used in assignments, initializations and
instantiations. The type of the target is ‘logic[15:0]’, while the type of
the source is ‘logic$[15:0]’.
Source Expression: x[3][15:0]”

If i replace declaration logic [15:0] y with logic y[15:0] error disappears. Now first declaration is packed array while second is unpacked. However, what i fail to understand is in the statement:
y = x[3][15:0], left hand side is array of 16 of type logic while right hand side is also an array of 16 bits of type logic. So I am not clear where is the incompatibility in the assignment.

thanks,
sunil

2

In reply to puranik.sunil@tcs.com:

Unpacked types are strongly typed, you need a cast.

typedef logic[15:0] uint16_t;
y = uint16_t'(x[3][15:0]);