Question about user defined constructor

SystemVerilog
1

Is it allowed to have use user-defined constructor inside a class instead of overriding “new()”?

class my_class;

function my_new();
$display("My user-defined constructor");
endfunction

endclass

my_class m1 = my_new();

vcs is throwing an error when i try to use “my_new()” constructor.

Identifier ‘my_new’ has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.

2

As far as the simulator is concerned “my_new” isn’t a constructor its just a function called “my_new”

SystemVerilog does not provide any mechanism to manually allocate memory, so there is no way to create your own constructor that would actually construct a new instance of the class object.

Can you elaborate on why you want to do this?
What about a user defined new method doesn’t meet your needs?

3

In reply to alexgran:

I was just trying out an experiment by writing a user-defined constructor. I read somewhere that this is allowed but i didn’t find anything related to this in LRM

4

In reply to Naven8:

You may be confused that there is a built-in constructor called new(), that the there is you do no define one yourself. Your user defined constructor must be called new().