Can someone explain why following code is giving different results when compiled in questa/modelsim?
LRM says that assigning value to input,output port are done using continuous assignment.
Each port connection shall be a continuous assignment of source to sink, where one connected item shall be
a signal source and the other shall be a signal sink. The assignment shall be a continuous assignment from
source to sink for input or output ports. The assignment is a non-strength-reducing transistor connection for
var logic x1,x2;
x1 = 1; x2 = 1;
#5 x1=0; x2 = 0;
#3 force m2.l1=1; force m2.l2 =1;
$display("Print values: %d ,%d ,%d, %d",x1,x2,m2.l1,m2.l2);
module mod2(input var logic l1,input wire logic l2);
In this example code questasim is outputting: 1,0,1,1
Whereas modelsim outputs: 0,0,1,1
Not sure why values are back propagating in case of questa. Can someone help me understand this?