Question about forcing module port

SystemVerilog
1

Hi Everyone,
Can someone explain why following code is giving different results when compiled in questa/modelsim?

LRM says that assigning value to input,output port are done using continuous assignment.

Each port connection shall be a continuous assignment of source to sink, where one connected item shall be
a signal source and the other shall be a signal sink. The assignment shall be a continuous assignment from
source to sink for input or output ports. The assignment is a non-strength-reducing transistor connection for
inout ports.

module mod1;
  var logic x1,x2;
  mod2 m2(.l1(x1));
  initial begin
    x1 = 1; x2 = 1;
    #5 x1=0; x2 = 0;
    #3 force m2.l1=1; force m2.l2 =1;
    $display("Print values: %d ,%d ,%d, %d",x1,x2,m2.l1,m2.l2);
    #5;
  end
endmodule
module mod2(input var logic l1,input wire logic l2);
endmodule

In this example code questasim is outputting: 1,0,1,1
Whereas modelsim outputs: 0,0,1,1

Not sure why values are back propagating in case of questa. Can someone help me understand this?

Thanks,
naven

2

Hi Naven,

The only difference between ModelSim and Questa is licensing, and for this piece of code, there should be no difference.

This public forum is not supposed to be for tool specific issues, and if you have some, they should go directly to Mentor support.

3

In reply to dave_59:

Sorry Dave, I was trying to find correct answer for the code which i pasted above with little bit explanation on why values are back propagating to the source.

4

In reply to Naven8:

The correct answer is 0,0,1,1 which is what I get when running Questa in the current version back to 10.0. The only chance that a force would propagate back to the source is when both upper and lower port connections are wires and the port get collapsed into a single wire.

5

In reply to dave_59:

Thanks Dave, Looks like your are referring to “section 23.3.3.7” in 2012 LRM. I will go through this section for further understanding.