Questa unexpected internal error: vgencode.c(207), verror (vopt-2064)

So this is less of a question and more of an FYI to anyone else who has this error.
Compiling completed successfully, but during vopt I received this error (on the line “Sending peripheral READ transaction”):

** Error: <path/file_name>: Questa has encountered an unexpected internal error: …/…/src/vlog/vgencode.c(207) <!cur_gen_stack_info || cur_gen_stack_info==stack_info>. Please contact Questa support…

** Error: (vopt-2064) Compiler back-end code generation process terminated with code 2.

The code is:

`define uvm_info_type_name(MSG,VERBOSITY) `uvm_info(get_type_name().toupper(), MSG, VERBOSITY)

class seq_base extends uvm_sequence #(item_base, item_base);

  `uvm_object_utils(seq_base)

  global_cfg global_cfg_h;

  bus_item   bus_item_h; // extends item_base
  bus_item   rsp_item_h; // extends item_base

  function new(string name = "seq_base");
    super.new(name);

    if (!uvm_config_db #(global_cfg)::get(get_sequencer(), get_type_name(), "global_cfg", global_cfg_h))
      `uvm_fatal_type_name("Cannot get() global_cfg from uvm_config_db. Have you set() it?")
  endfunction : new

  task body();
    `uvm_error_type_name("You forgot to override the base sequence!")
  endtask : body

endclass : seq_base

class slave_seq extends seq_base;

  `uvm_object_utils(slave_seq)

  function new(string name = "slave_seq");
    super.new(name);
  endfunction // new

  task body();
    `uvm_info_type_name("Starting sequence...", UVM_LOW)

    fork
      forever begin : send_trans
        wait(global_cfg_h.reset_isasserted == 1'b0);

        if (global_cfg_h.test_done == 1'b0) begin
          `uvm_info_type_name("Sending peripheral READ transaction", UVM_LOW)
          `uvm_do_with(bus_item_h,  { trans_type == READ; })
          get_response(rsp);
          $cast(rsp_item_h, rsp);
          rsp_item_h.print();
        end

        if (global_cfg_h.test_done == 1'b1)
          break;
        
        #1ns; // delay so forever doesn't hang
      end
      
      begin : check_global_cfg
        wait(global_cfg_h.test_done == 1'b1);
        #100ns; // give the driver a chance to return the sequence-in-progress nicely
        disable send_trans;
      end
    join_any
    
    `uvm_info_type_name("Sequence completed!", UVM_LOW)

  endtask : body

endclass : slave_seq

I found that by changing the macro to be:

`define uvm_info_type_name(MSG,VERBOSITY) `uvm_info(type_name.toupper(), MSG, VERBOSITY)

that the error goes away!
If anyone can explain why, it would be much appreciated!

SystemVerilog does not allow chaining of method calls. However, some tools do allow certain cases depending on which version you have.