Query for Modeling Ownership

SystemVerilog
1

Dear All,

This question is no correct answer but. I want to know that how verification engineer have the scope for modeling.
Basically In Analog, In DSP, we have faced lots of circumstance for verification. Especially, at that time, we need the modeling for verification.
Here, my question is that, Who have the ownership for modeling.
In my opinion, The ownership has to be to designer not verification engineer. because that model can’t have a projection of designer’s idea.

Could you please share of your Idea?

2

In reply to UVM_LOVE:

This is not the correct question. In many cases, the designer and verification engineer is the same person. So the question should instead be how to ensure the verification model does not make the same mistakes as the design? This question holds whether there is one person, or split teams.

Ideally having a written requirements document intend of ideas in someone’s head can work wonders. The key to verification is having two different models addressing the same set of requirements.