Hi,
I have a scenario where I need to write an assertion. Please help me. I have 2 interrupts I1(highest priority) and I2(low priority). Once I1 occurs, there is some functionality to be done and for I2 also the same. Suppose When I1 is running, in between I2 has come. After I1 finishes only I2 should start and execute that assertion. How to handle such type of situation. Please help me out
In reply to Anudeep J:
I have a scenario where I need to write an assertion. Please help me. I have 2 interrupts I1(highest priority) and I2(low priority). Once I1 occurs, there is some functionality to be done and for I2 also the same. Suppose When I1 is running, in between I2 has come. After I1 finishes only I2 should start and execute that assertion. How to handle such type of situation. Please help me out
[Ben] There are several aspects to these assertions:
For your problem, if while the processing of i1 occurs, i2 occurs, you want to process the lower priority i2 to start when the high priority finishes; in other words, you do not want the higher priority i1 to restart because it is of higher priority.
I started something for you, but I am not really happy with it because I did not write assertions for the illegal conditions; also, I am not sure if my legal assertions are OK. I am providing my code only as a guide. You may want to consider using FSMs written in SystemVerilog as the support logic, and then write the legal and illegal assertions. I’ll let you do that. I hope this guide will help you. Code is available at
http://systemverilog.us/i1i2.sv
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk, i1, i2; //
bit done_i1, done_i2;
// Need to know when i1 or i2 can go to completion once initiated.
bit go_i1=1'b1, go_i2=1'b1; //
bit i1_initialted, i2_initialted;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
function void set_go_i1(bit x);
go_i1=x;
endfunction
function void set_go_i2(bit x);
go_i2=x;
endfunction
function void set_i1_intitiated(bit x);
i1_initialted=x;
endfunction
function void set_i2_intitiated(bit x);
i2_initialted=x;
endfunction
ap_i1: assert property(
$rose(i1) |-> go_i1[->1] ##0
(1, set_go_i1(1'b0), set_go_i2(1'b0), set_i1_intitiated(1'b1))
##1 // disable the go of i1, i2
done_i1[->1] ##0 !i2_initialted[->1]
##0 (1, set_i1_intitiated(1'b0), set_go_i1(1'b1), set_go_i2(1'b1)) );
ap_i2: assert property(
$rose(i2) |-> go_i2[->1] ##0
(1, set_i2_intitiated(1'b1)) ##1 // disable the go of i2
done_i2[->1] ##0 (1, set_i2_intitiated(1'b0), set_go_i1(1'b1)) );
initial begin
repeat(200) begin
@(posedge clk);
if (!randomize(i1, i2, done_i1, done_i2) with
{ i1 dist {1'b1:=1, 1'b0:=17};
i2 dist {1'b1:=1, 1'b0:=17};
done_i1 dist {1'b1:=1, 1'b0:=20};
done_i2 dist {1'b1:=1, 1'b0:=20};
}) `uvm_error("MYERR", "This is a randomize error")
end
$finish;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us