Hi,
Can anybody explain me why we will declare property inside clocking block .
clocking cb_with_input @(posedge clk);
input a;
property p1;
a;
endproperty
endclocking
Thanks,
Sayam
In reply to SAYAM RAJA:
Property declarations within a clocking block is rarely used. as to why we will declare property inside clocking block, it’s because the clocking for the assertion is valid for all properties and sequences defined within this clocking block.
SystemVerilog also allows for the specification of input and output skews. Input (or inout) signals are sampled at the designated clock event. If an input skew is specified then the signal is sampled at skew setup time units before the clock event. Similarly, output (or inout) signals are driven skew hold simulation time units after the corresponding clock event. An example of a skew definition is shown below:
An example of a skew definition is shown below:
clocking master_clock @(posedge clk);
//input #1ps address; // setup time
input #5 output #6 address, data; // setup and hold time
property P;
address==8'HFF |=> data==8'H00;
endproperty : P
// input address sampled 5ns before posedge clk, and data sampled 5ns before posedge clk)
endclocking : master_clock
1800’2017 imposes rules on properties defined in clocking block. From 1800: The default clocking event does not apply to a sequence or property declaration except in the case that the declaration appears in a clocking block whose clocking event is the default.
b) The following rules apply within a clocking block:
- No explicit clocking event is allowed in any property or sequence declaration within the
clocking block. All sequence and property declarations within the clocking block are treated as though the clocking event of the clocking block had been written explicitly as the leading clocking event. - Multiclocked sequences and properties are not allowed within the clocking block.
- If a named sequence or property that is declared outside the clocking block is instantiated within the clocking block, the instance shall be singly clocked and its clocking event shall be identical to that of the clocking block.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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