Proper way to do addition of operands with width mismatch

SystemVerilog
,
1

In the below code WIDTH_B=8 and WIDTH=4
b is input, sum_next is output and sum is a logic variable.
is this code synthesis friendly?
is there a better way to do the addition when there is a width mismatch in the operands?



        input logic   [WIDTH_B-1:0] b;
        output logic  [WIDTH-1:0] sum_next;
        logic  [WIDTH-1:0]  sum;

       always_comb
        begin
            sum_next = sum + b;
        end
2

In reply to svishnu:
In 2002 I wrote the book Real Chip Design and Verification Using Verilog and VHDL, and in that book I address the general topic of doing arithmetic in Verilog and VHDL.
The following is an extraction of pages from that book that provides an explanation of those concepts with lots of examples.

The code examples referenced in the book are at:
http://systemverilog.us/vf/arith_verilog.zip

Hopefully, that will provide answers for you as your question really involved your thorough understanding of how arithmetic is handled in Verilog (and SystemVerilog), including the automatic extension of bits for unmatched sized operands.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us