i want to learn System verilog for verification. for this can you suggest me few projects from which i can learn practically. i have been referring SV LRM but i feel theory isnt fetching me perfection in the concepts. so if you can suggest me with more efficient ways please share with me it will be helpful for me.
In reply to sreelaxmi:
i want to learn System verilog for verification. for this can you suggest me few projects from which i can learn practically. i have been referring SV LRM but i feel theory isnt fetching me perfection in the concepts. so if you can suggest me with more efficient ways please share with me it will be helpful for me.
There are many aspects to verification, and that includes the definition of the driving stimuli, the coverage, assertions that the DUT/subsystem is working per requirements and assumptions.
There are many sources that provide examples and tutorials. A short list:
- https://verificationacademy.com/ (see the sub-links, lots of info here!)
- Several books on SystemVerilog (spelled as one word BTW) and assertions and formal verification. On assertions I provide the book SVA Handbook 4th Edition, 2016 ISBN 978-1518681448; it has many complete examples.
- UVM is gaining popularity in defining the verification environment
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115