Procedural and Cont assign on ref ports

SystemVerilog
1

Hi,

What will be the output of the following code.


module childMod(input wire logic [31:0] a, output var [31:0] val);

  assign val = a + 1;
  childMod1 ch2(a, val);

  always @(val) begin
      $display($time(), ": Always [%m] val = %d, a = %d", val , a);
  end

endmodule

module childMod1(a,val);

   input wire logic [31:0]a;
   ref logic[31:0]  val;

   initial  begin
     #1 val = 10; //should not allow to have procedural and continous assign
   end

endmodule

module top();

   logic [31:0] a;
   logic [31:0] val;

   logic [31:0] r_a;
   logic [31:0] r_b;

   assign  a = r_a;

   childMod ch1(a, val);

   initial begin
     #1 r_a = 10;
   end

   always @(val) begin
      $display($time(), ": Always [%m] val = %d, a = %d", val , a);
   end

endmodule
2

In reply to SumitGoel:

This should be illegal. In any case, I can not see any good reason to be using a ref port with a continuous assignment. The purpose of a ref port is to have a shared variable procedurally accessible to multiple modules.