Problem with interface

SystemVerilog
1

hi all,

interface inf_generic #(parameter test = "")(input bit clk); // generic interface

if ((test) =="first_interface ")
	first_interface f_intf(clk);

else if  ((test) =="second_interface ")
	second_interface s_intf(clk);

endinterface : inf_generic

when i call my interface in my module :


module test_harness();

  timeunit 1ns;
  timeprecision 1ns;
  // clock generator
  //
  bit PCLK;
  always #5 PCLK = ~PCLK;

  // test access interface
  //
  //APB_test_intf 	TB_intf(PCLK);
  // APB_bfm			TB_bfm(TB_intf);
	inf_generic #(.test("first_interface")) inf_g(PCLK);


  
  // DUT (simple behavioural model)
  
  APB_dummy DUT(
    .PCLK   (PCLK),
    .PENABLE(inf_g.f_intf.a),
    .PSEL   (inf_g.f_intf.b   ),   //   Connect DUT ports to
    .PWRITE (inf_g.f_intf.c ),   //   appropriate signals in the
    .PADDR  (inf_g.f_intf.d  ),   //   test access interface
    .PWDATA (inf_g.f_intf.e ),
    .PRDATA (inf_g.f_intf.f )
  );
  endmodule

i have this error and i don’t understand why

Failed to find 'f_intf' in hierarchical name 'inf_g.f_intf.f'

when i do not use if statement i don’t have this error.

I am new to systemVerilog.

2

In reply to bartolo:

This is because name of interface instance in port connection (ing_g) differs from interface instance declaration (inf_g).

Change port connection as below.


  APB_dummy DUT(
    .PCLK   (PCLK),
    .PENABLE(inf_g.f_intf.a),  // not ing_g but inf_g
    .PSEL   (inf_g.f_intf.b   ), 
    .PWRITE (inf_g.f_intf.c ),   
    .PADDR  (inf_g.f_intf.d  ), 
    .PWDATA (inf_g.f_intf.e ),
    .PRDATA (inf_g.f_intf.f )
3

In reply to kitanisi:

hi,

sorry I made a mistake when I copied paste ,I have the same port connection as you

4

In reply to bartolo:

Two issues:

  1. The parameter passed into inf_generic() has no space at the end of the string, whereas in the interface, the strings that you are comparing have spaces at the end. This results in a mis-match, although this may be a typo.

  2. Your code is creating generate blocks, which add a layer of hierarchy. You need to account for this hierarchy in your interface references.

5

In reply to cgales:

thank you for your reply,
I tried with one interface,

when i try

interface inf_generic #(parameter test = "")(input bit clk); // generic interface
 
first_interface f_intf(clk);
 
 
endinterface : inf_generic

my program work but when i try

interface inf_generic #(parameter test = "")(input bit clk); // generic interface
 
if ((test) =="first_interface ")
	first_interface f_intf(clk);
 
endinterface : inf_generic

I have the same error.

when I remove the dut and I put a display in my if , I see my display in the transcript

Sorry for my bad english.

6

In reply to bartolo:

As I said above, using an ‘if’ statement implicitly creates a generate block.

To reference the interface, you will need to use:

inf_g.genblk1.f_intf.a

Notice the ‘genblk1’ in the hierarchy path. Since you don’t name the generate block, the hierarchy name will vary depending on the simulator. You should use a named generate statement.

7

In reply to cgales:

thank you for your reply^^.