Problem with Inheritence

This is the following piece of code:

class Transaction;
rand bit [31:0]dst,src,data[8];
bit [31:0]crc;
function void calc_crc;
crc = dst^src^data.xor();
endfunction
function void display_crc;
$display(“The value of crc=%0d for the following values dst=%0d,src=%0d,data=%0p”,crc,dst,src,data);
endfunction
endclass

`include “Transaction.sv”
class Nearby extends Transaction;
constraint c_dst { dst inside {[src-10:src+20]};
}
endclass

`include “Nearby.sv”
class Generator;
mailbox gen2drv;
Nearby tr1;
function new(input mailbox gen2drv);
this.gen2drv = gen2drv;
tr1 = new();
endfunction
task run();
forever
begin
assert(tr1.randomize());
gen2drv.put(tr1);
end
endtask
endclass

`include “Nearby.sv”
class Driver;
mailbox gen2drv;
Nearby tr2;
function new(input mailbox gen2drv);
this.gen2drv = gen2drv;
endfunction
task main();
forever
begin
tr2 = new();
gen2drv.get(tr2);
tr2.calc_crc;
end
endtask
endclass

include "Nearby.sv" include “Environment.sv”
class test;
Environment env;
initial
begin
env = new();
env.build();
begin
Nearby nb;
nb = new();
env.gen.blueprint = nb;
end
env.run();
env.wrap_up;
end
endclass

include "Generator.sv" include “Driver.sv”
class Environment;
Generator gen;
Driver drv;
mailbox gen2drv;
function void build();
gen2drv = new();
gen = new(gen2drv);
drv = new(gen2drv);
endfunction
task run();
fork
gen.run();
drv.main();
join_none
endtask
task wrap_up;
endtask
endclass

I get 2 error saying :
Typedef ‘Nearby’ multiply defined.
Typedef ‘Transaction’ multiply defined.

Can any one help me with this.

In reply to Ravi007:

Use the conditional compilation. Like given below:

`ifndef <class name>
`define <class name>
...
... //Here goes the code
...

`endif

In reply to sunils:

Don’t use conditional compilation `ifdefs. They are messy and indicate that the user’s code is poorly organized.

Instead, you should be using SystemVerilog Packages. You compile your classes into a package and import them when required. There is a lot of discussions about the proper use of packages on Verification Academy.