Probing VHDL signal in Verilog Module

We have a hierarchy “verilog_module1.vhdl_module.verilog_module2.param” in testbench “verilog_tb”. So I want to override param in verilog_tb. Let me know the possible ways to achieve “param” overriding.

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You can certainly pass Verilog parameters to VHDL generics and VHDL generics can be passed to Verilog module parameters. The Questa examples directory can show you mixed language instantiations.