Printing the incorrect frequency when assertion for clock period check fails

SystemVerilog
1 
property clk_assert (clk_a, rst, en );

@(posedge clk_a) disable iff( )
                                                                                        
('1, current_time = $realtime) |=> ( (($realtime - current_time)  <= max_period ) && 
                                      ($realtime - current_time)  >= min_period )
                                    );
clk_check: assert property (clk_assert (   clk_a, rst, en     )) 
                           else $error($time,"%0t tx_bist_frequecny is incorrect");

I want to print the $realtime - current time so that i can see what frequency it is when it fails? Is there way to do it using display statements or other methids?

2

In reply to abhi9891:


module m2; 
  bit rst, en=1, clk_a; 
  realtime err_period, max_period=11ns, min_period=9ns; 
  function void wr_time(realtime t);
    err_period=t;
  endfunction

  property clk_assert (clk_a, rst, en );
     realtime current_time, v; 
  @(posedge clk_a) disable iff(rst) 
  ('1, current_time = $realtime) |=> (1, v=$realtime - current_time,  wr_time(v)) ##0 
                                        v <= max_period  && v  >= min_period;
endproperty 
clk_check: assert property (clk_assert ( clk_a, rst, en ))
                           else $error("%0t tx_bist_frequecny is incorrect %t", $realtime, err_period); 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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3

Hi Ben ,

I am trying to check the phase difference between 2 clocks are exactly aligned or not on every posedge of clock1 .

Expected is period variable in below . i am using -timescale 100fs/100fs

      realtime period = 41.7 ;

	property period_chk(start,stop, period);
		realtime start_time,v;
		@(start) 
		(1,start_time = ($realtime * 1000)) |->
		@(stop)
		(1,v=  ($realtime * 1000) -start_time, wr_time(v)) ##0 v == period;  
		
	endproperty

	property phase_diff_ck(enable, ck1,ck2);
		@(ck1)
		($rose(enable)) |-> period_chk(posedge ck1, posedge ck2, period) 
	endproperty 

      assert property(phase_diff_ck(enable,clk1,clk2))
else `uvm_error("ASSERTIon FAILURE",$sformatf(" Error in Phase difference b/w CK1 and CK2 Expected=%t || Observed=%t ",period , err_period))

i am getting the following error ,

Error in Phase difference b/w CK1 and CK2 Expected= 41700000 || Observed= 41700000

If i change the

realtime period = 41700000

then i get following error
Error in Phase difference b/w CK1 and CK2 Expected= 41700000000000 || Observed= 41700000

Can you please analyze and let me know where i am going wrong .

Rohit

4

It looks like you need to add an acceptable tolerance because of the resolution of the real type. Something like:
v >= period - 1fs || v <= period +1fs

5

Ben , need to know why without tolerance it wont work .
with real datatype - what i have observed is always we need to add the tolerance range for checker .

6

From

Understanding real, realtime and shortreal variables of SystemVerilog
This post will help you to understand the difference between real, realtime and shortreal data types of SystemVerilog and its usage.

We faced some issue with real and realtime variable while writing a timing check.
Below is a simplified example of that check.

`timescale 1ns/1fs;
module test; 
  real a,b;  
  realtime t1, t2;

initial 
begin 
  #1ns;
  t1 = $realtime;
  #1.8ns;
  t2 = $realtime;
  b = 1.8;
  a = t2 - t1; 

  if(a == b)
    $display("PASS a = %f b = %f", a,b);
  else
    $display("FAIL a = %f b = %f", a,b);

end 
endmodule 

/* and here is what we got the display

FAIL a = 1.800000 b = 1.800000  

How that happened !!! is really 1.800000 != 1.800000  !!!!

Now let's try something else, instead of using real we use shortreal */


`timescale 1ns/1fs;
module test; 
  shortreal a,b;  
  realtime t1, t2;

initial 
begin 
  #1ns;
  t1 = $realtime;
  #1.8ns;
  t2 = $realtime;
  b = 1.8;
  a = t2 - t1; 

  if(a == b)
    $display("PASS a = %f b = %f", a,b);
  else
    $display("FAIL a = %f b = %f", a,b);

end 
endmodule 

/* Now the result was as expected !!

PASS a = 1.800000 b = 1.800000

To understand this lets go to SystemVerilog LRM. As per LRM 

The real data type is from Verilog-2001, and is the same as a C double. 
The shortreal data type is a SystemVerilog data type, and is the same as a C float. */
7

Thank you Ben for clarifying ,