I need a small clarification regarding keyword - “predict”. And how is it related to set/get keywords ?
For instance :-
rd_val = abc_3.BAR_OFFSET101.predict(32’hFFFF_FFFF);
$display(“debug: rd_val is %x”, rd_val);
Upto my understanding,from the above piece of code I am trying to predict the value of rd_val as FFFF_FFFF, please correct me if I am wrong.
same thing we can do with set/get keywords.
So how does it makes the difference .
NOTE : These[predict , set/get] are methods .
Thanks
arpit
“predict”, “set”, “get” are not SystemVerilog keywords; they are methods of the uvm_reg class. You have access to the UVM documentation as well as the source code to see the difference.
The uvm_reg class libraries create many different shadow copies of an actual DUT register.
Some routines are used to modify the values in those shadow copies, and others generate sequences to either modify the shadow copies, the DUT, or both.
I had started to look into the UVM source codes from last 3 days only but I am sorry i am not able to find
the specific scenario to describe the usage of predict as compared with set/get.
If possible can you point out any specific doc or link .
predict - used to define what would be the value of the register (as per attributes) when we are trying to write the value mentioned as arguement.Would update the RAL copy of the register value, but does not touch the actual register. get - would return of RAL value of the register. set - would set the RAL value of the register, irrespective of attributes.
This is just a very brief decription. Please refer to the source code for actual details.
Note: As per my understanding, perdict does not return the value. Just returns success or failure.