Post randomization order within nested class

SystemVerilog
, ,
1

Please consider the code below.

class inside_c;
    function void  post_randomize();
        $display("INSIDE_C- post_randomize");
    endfunction
endclass

class inside_c_1;
    function void  post_randomize();
        $display("INSIDE_C_1- post_randomize");
    endfunction
endclass


class ex_child;
    rand inside_c_1 ins_obj_1;
    rand inside_c ins_obj;
    function new;
        ins_obj = new;
        ins_obj_1 = new;
    endfunction
    function void  post_randomize();
        $display("EX-CHILD- post_randomize");
    endfunction
endclass

module test;
    ex_child m_twoD;
    initial begin
        m_twoD = new;
        m_twoD.randomize();
    end
endmodule

The output is

EX-CHILD- post_randomize
INSIDE_C_1- post_randomize
INSIDE_C- post_randomize

I expected post random of children’s to be called before the parent. Does anyone know why is the order so? Also, if I want to use parent’s post-random to alter its member elements based on child’s value from its post-random, Is it possible (Without doing delays in post-random function of parent (with fork-join_none))

2

In reply to sharatk:

The LRM does not specify an order, but I would expect the parent to be called first if using a depth-first traversal.

If you need a specific ordering, then use some function other than post_randomize(). Or at least have ex_child::post_randomize() call another function inside each child class.

3

In reply to dave_59:

Thanks Dave. All simulator at eda playground seem to do parent first. I just felt its counter intuitive