Hello I was trying to connect a DUT to interface and used logic type in interface and connected them to DUT signals. DUT signals inside DUT are declared as wire. Compilation is giving error
Error-[PCTM] Port connection type mismatch
The following expression is illegally connected to port “pkt_tx_data” of
module “xge_mac”, instance “dut”. The type of the port does not match that
of the port connect.
Code is as below. I have connected module port declared as wire to logic types declared in interface before but did not face this issue before.
xge_mac dut(
// Outputs
.pkt_rx_avail (i_pkt_rx_interface.pkt_rx_avail),
.pkt_rx_data (i_pkt_rx_interface.pkt_rx_data[63:0]),
.pkt_rx_eop (i_pkt_rx_interface.pkt_rx_eop),
.pkt_rx_err (i_pkt_rx_interface.pkt_rx_err),
.pkt_rx_mod (i_pkt_rx_interface.pkt_rx_mod[2:0]),
.pkt_rx_sop (i_pkt_rx_interface.pkt_rx_sop),
.pkt_rx_val (i_pkt_rx_interface.pkt_rx_val),
.pkt_tx_full (i_pkt_tx_interface.pkt_tx_full),
.wb_ack_o (i_wishbone_interface.wb_ack_o),
.wb_dat_o (i_wishbone_interface.wb_dat_o[31:0]),
.wb_int_o (i_wishbone_interface.wb_int_o),
.xgmii_txc (i_xgmii_tx_interface.xgmii_txc[7:0]),
.xgmii_txd (i_xgmii_tx_interface.xgmii_txd[63:0]),
// Inputs
.clk_156m25 (clk_156m25),
.clk_xgmii_rx (clk_xgmii_rx),
.clk_xgmii_tx (clk_xgmii_tx),
.pkt_rx_ren (i_pkt_rx_interface.pkt_rx_ren),
.pkt_tx_data (i_pkt_tx_interface.pkt_tx_data[63:0]),
.pkt_tx_eop (i_pkt_tx_interface.pkt_tx_eop),
.pkt_tx_mod (i_pkt_tx_interface.pkt_tx_mod[2:0]),
.pkt_tx_sop (i_pkt_tx_interface.pkt_tx_sop),
.pkt_tx_val (i_pkt_tx_interface.pkt_tx_val),
.reset_156m25_n (reset_156m25_n),
.reset_xgmii_rx_n (reset_xgmii_rx_n),
.reset_xgmii_tx_n (reset_xgmii_tx_n),
.wb_adr_i (i_wishbone_interface.wb_adr_i[7:0]),
.wb_clk_i (wb_clk_i),
.wb_cyc_i (i_wishbone_interface.wb_cyc_i),
.wb_dat_i (i_wishbone_interface.wb_dat_i[31:0]),
.wb_rst_i (wb_rst_i),
.wb_stb_i (i_wishbone_interface.wb_stb_i),
.wb_we_i (i_wishbone_interface.wb_we_i),
.xgmii_rxc (i_xgmii_rx_interface.xgmii_rxc[7:0]),
.xgmii_rxd (i_xgmii_rx_interface.xgmii_rxd[63:0]));
Interface is declared as below. Others interface follows same convention.
interface pkt_tx_interface(input bit clk_156m25, input logic reset_156m25_n);
logic pkt_tx_data[63:0];
logic pkt_tx_val;
logic pkt_tx_sop;
logic pkt_tx_eop;
logic pkt_tx_mod[2:0];
logic pkt_tx_full;
endinterface