Polymorphism basic question

SystemVerilog
1

Below is my example of polymorphism example. my expected results are not matching with the simulated one.
after reading LRM also I am not getting a crystal clear explanation about the simulated results.

Can any body help?

Expected results:

Inside child class:: value of a:-> 100
Inside Parent class:: value of a:-> 10

class base;
  int a=10;

  task display ();
         $display(" Inside Parent class:: value of a:-> %0d", a);
        endtask
endclass

   class child extends base ;
         task display ();
          a =100;
          $display(" Inside child class:: value of a:-> %0d",a);
         endtask
     
       function new();
		super.new();
      endfunction
     
    endclass
      
     module main ;
        child my_child;
        base my_base;
          
          initial
          begin
              my_child = new();
              my_base = my_child;
              my_child.display();
              my_base.display();
          end
      endmodule

Simulated results

Inside child class:: value of a:-> 100
Inside Parent class:: value of a:-> 100

2

In reply to shailendradwivedi:

There is only one variable called ‘a’ and you set it to 100 when you called my_child.display(). If you reverse the order of calls to display(), you would get the result you are looking for.

Please see OOPS terminologies in SV | Verification Academy

3

In reply to dave_59:
Hi Dave,

Thanks for helping.

in the same example, my question is why the value of a is initialized with 100 because on parent class it is initialized with different value

4

In reply to shailendradwivedi:

You initialized a=10 when constructing the extended class, but then you later assign it to 100 when calling child::display.