Polymorphism

SystemVerilog
1

Hi ,

 
1]
class    base;
  
  
  int addr;

   function void method(int data);
      $display("contents %0d",data);
  endfunction

  function void method(real data);
      $display("contents %0f",data);
  endfunction

endclass


module tb();

   base  b_h;
  
   initial
      begin 
      b_h =new;
      b_h.method(1);
      b_h.method(2.2);
      end
endmodule

The normal function overloading 1], gives me an error , so tried to implement static polymorphism using parameterised class below


class    base#(type t=int);
  int addr;

  function void method(t data);
      $display("contents %0f",data);
  endfunction

endclass


module tb();

  base#(int)   b_h;
  
  base #(real)  b_h2;
   initial
      begin 
      b_h =new;
      b_h.method(3);
      b_h2=new;
      b_h2.method(1.3);
      end
endmodule

Can this be considered as static polymorphism / operator overloading in sv.

Thanks in Adv

2

In reply to bl4ckp3rl :

Yes, you may want to read: Compile-time Polymorphism in SV | Verification Academy