Hello dave,
Can you please explain about return value of randomization?
Why we need to pass assertion to know the return value of randomize() ?
Can you please explain with an example?
In reply to dinakarkuchi9:
Hello dave,
Can you please explain about return value of randomization?
Why we need to pass assertion to know the return value of randomize() ?
Can you please explain with an example?
The result of the randomize function is false if the randomization fails.
In most simulation cases it is recommended to disable assertion checking until the testing environment is stabilized. Once that point is reached, assertion checking can be enabled.
When the assertions are disabled, the assert(randomize(object)) will be disabled, and no checks will be performed, the randomization of the desired variables will not take effect. Instead use:
if(!randomize(var1, var2, var3)) $error("randomization failure"); // list of variables
// If classes with rand variables are used, then use : (See Ch9/consecutive.sv for an example)
if (!class_instance.randomize()) $error("randomization failure"); // without UVM
if (!class_instance.randomize()) `uvm_error("MYERR", "error message"); // with UVM
Below is an example with a randomization failure.
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
int a, b;
initial begin
repeat(2) begin
if (!randomize(a) with
{ a < 10; a >11; }
) `uvm_error("MYERR", "This is a randomize error")
end
$stop;
end
endmodule
// sim result
UVM_ERROR asn2rdn.sv(9) @ 0: reporter [MYERR] This is a randomize error
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
In reply to ben@SystemVerilog.us:
Hello Ben,
Thanks for the reply but.i know what you discussed how randomization fails. Please go through the question properly.
Thank you.
In reply to dinakarkuchi9:
In reply to ben@SystemVerilog.us:
Hello Ben,
Thanks for the reply but.i know what you discussed how randomization fails. Please go through the question properly.
Thank you.
I would go to the question “properly” if the question was less ambiguous.
Can you please explain about return value of randomization?
Why do we need to pass assertion to know the return value of randomize() ?
Are you asking why we need the assert statement? If so, then
in assert(randomize(object)) the randomize function is called from within the assert statement, and the return value is used in the assertion.
Regardless of how the randomize function is used, the return of that function is generally used to check on the validity or success of the function.
Please clarify your question.
Ben SystemVerilog.us