Pattern Generation

I have a 50 bit variable, I want to generate a pattern as shown in example under. How do I write a constraint for it.

For Example
rand bit[10:0] var; (Taking an example of 10 bit variable actual pattern needed is for a 50 bit variable)

Pattern
1000000000
1100000000
1110000000
1111000000
1111100000
1111110000
1111111000
1111111100
1111111110
1111111111

Is there really a need to use constraints for something that can easily be done with a function call? Also, if you can write constraints, what should the randomize function do when all bits are ones?
Ben

In reply to nishitk:

rand bit[10:0] varb = 11'b10000000000;
constraint pattern { varb == const'( {1'b1, varb[10:1]} ); }

In reply to dave_59:

Why the need for the const?

In reply to ben@SystemVerilog.us:
A const cast means treat the expression as a constant value (I.e. non-random) value. The expression gets evaluated before randomization and is treated like a state variable.

In reply to dave_59:

It helps. Thanks Dave !

In reply to dave_59:

In reply to nishitk:

rand bit[10:0] varb = 11'b10000000000;
constraint pattern { varb == const'( {1'b1, varb[10:1]} ); }

i am getting this error plz help me OUT
// code here
class packet;
rand bit[10:0] varb = 11’b10000000000;
constraint pattern { varb == const’( {1’b1, varb[10:1]} ); }
endclass

module constr_blocks;
initial begin
packet pkt;
pkt = new();
repeat(10) begin
pkt.randomize();
$display(“\t value = %0d”,pkt.varb);
end
end
endmodule

output:ERROR VCP7501 “Undeclared type: const.” “testbench.sv” 5 59

In reply to Rohi_417:

It looks like your tool has not implemented a const cast. Maybe you have an older version. Please contact your vendor for support.